Technical Field
The present disclosure relates to resistive memories, and more generally to memories in which each memory cell comprises a select transistor and a variable impedance element which can have several different states detectable by an impedance measurement. Depending on whether the element can keep its state with or without power supply, the memory is volatile or non-volatile.
Description of the Related Art
Thus, several types of resistive memories are being developed. In conductive-bridging random access memories (CBRAM), the variable impedance element comprises two electrodes and a thin layer of solid electrolyte arranged between the electrodes. Under the effect of biasing the element, metal ions migrate from one of the two electrodes and from the electrolyte to the other electrode, and form filaments which reduce the electrical resistance of the element.
Resistive RAM memories (RRAIVI or ReRAM) comprise a dielectric element which can be forced to be conductive in a reversible manner by forming conductive filaments obtained by applying a sufficiently high voltage.
In ferroelectric RAM memories (FeRAIVI or FRAM), the variable impedance element comprises a capacitor the dielectric of which is a ferroelectric material in which magnetic dipoles can be oriented along the field lines of an electric field formed between the electrodes when the capacitor is charged. When the capacitor discharges, the dipoles keep their orientation.
The variable impedance element of MRAM (Magnetoresistive RAM) memories comprises two plates made of ferromagnetic material which can produce an electric field, separated by a dielectric film. One of the plates is a permanent magnet, whereas the other plate generates a magnetic field which can be modified by an electric current. The state of the memory cell is read by an impedance measurement.
Certain so-called “phase change” memories use as variable resistive element a material which can take an amorphous or crystalline state under the effect of a temperature increase.
FIGS. 1A, 1B schematically represent a cross-section of a semiconductor substrate SUB in which a memory cell MC comprising a variable impedance element VZ is formed. FIG. 1A is a longitudinal cross-section along the plane AA′ indicated on FIG. 1B, and FIG. 1B is a transverse cross-section along the plane BB′ indicated on FIG. 1A. The memory cell MC comprises a select transistor comprising a gate GT, drain DDP and source SDP regions on either side of the gate GT, and a channel region beneath the gate GT between the drain DDP and source SDP regions. The gate GT is produced in a layer made of polycrystalline silicon formed on an insulating layer deposited on the substrate SUB. The regions DDP, SDP are formed by implanting dopants in the substrate SUB on each side of the gate GT. The memory cell MC is covered by a dielectric insulating material IL. The source region SDP is coupled to a reference line RL through a contact passing through the insulating layer IL. The gate GT forms a selection line SL extending in parallel to the reference line RL. The variable impedance element VZ is formed in the insulating layer IL and is coupled to the drain region DDP through a contact formed in the insulating layer IL. The variable impedance element VZ is coupled to a data line DL formed on the surface of the layer IL through a contact formed in the insulating layer IL. The data line DL is perpendicular to the reference RL and selection SL lines. The memory cell is isolated from the other memory cells by isolating trenches STI1 parallel to the gate GT, and isolating trenches STI2 perpendicular to the gate GT.
FIG. 2 represents the electric circuit of a part of a memory array comprising memory cells such as the memory cell MC represented on FIGS. 1A, 1B. The memory array comprises selection lines SL, reference lines RL parallel to the selection lines SL and data lines DL perpendicular to the selection lines SL and to the reference lines RL. Each memory cell MC comprises a select transistor ST comprising a conduction terminal (source or drain) connected to a terminal of a variable impedance element VZ the other terminal of which is connected to one of the data lines DL. The other conduction terminal of the select transistor ST is connected to one of the reference lines RL, and the gate terminal of the transistor ST is connected to one of the selection lines SL.
To reduce the surface area occupied by each memory cell, it has been proposed to produce the memory cells in pairs, sharing a same conduction region connected to a reference line. Thus, FIG. 3 represents a longitudinal cross-section of a pair of memory cells MC1, MC2 each comprising a select transistor ST1, ST2. The transistors ST1, ST2 share a same conduction region SDP connected to a reference line RL. Each select transistor ST1, ST2 comprises a gate GT, and another conduction region DDP connected to a variable impedance element VZ further connected to a data line DL common to the two memory cells MC1, MC2. Isolating trenches STI1 are produced between each pair of memory cells.
To reduce the surface area occupied by each memory cell, it has also been proposed to replace the isolating trenches ST1 with CMOS transistor gates formed on the substrate and connected to the ground, the substrate also being connected to the ground. Thus, FIG. 4 represents a memory cell MC3 identical to the memory cell MC, but in which the isolating trenches STI1 are replaced with transistor gates IG which may be narrower than the trenches STI1, and formed on a layer of gate oxide GO deposited on the substrate.
It is desirable to further reduce the substrate surface area occupied by a memory cell comprising a variable impedance element.